In FIG. 1 a prior art insulated gate bipolar transistor (IGBT) is shown as known from EP 0 795 911 A2. The prior art device comprises an active cell with layers of different conductivity types in the following order between an emitter electrode 2 on an emitter side 22 and a collector electrode 25 on a collector side 27 opposite to the emitter side 22: an (n+) doped source layer 3, a p doped base layer 4, which contacts the emitter electrode 25, an n doped enhancement layer 95, an (n−) doped drift layer 5, an (n+) doped buffer layer 55 and a p doped collector layer 6.
A trench gate electrode 7 is arranged on the emitter side 22, which comprises a gate layer 70 and a first electrically insulating layer 72, which surrounds and thus separates the gate layer 70 from the drift layer 5, base layer 4 and the source layer 3. A second insulating layer 74 is arranged between the gate layer 70 and the emitter electrode 2. The trench gate electrode 7 extends from the emitter side 22 up to a trench depth 77, at which a trench bottom 76 is arranged, which has trench lateral sides 75 extending from the trench bottom 76 to the emitter side 22. A p doped first protection pillow 8 covers the trench bottom 76.
As described in EP 0 795 911 A2 the prior art device is created by first implanting and diffusing an N-dopant for the creation of the enhancement layer 95. The enhancement layer 95 has a higher doping concentration than the drift layer 5. Afterwards, a P-dopant is implanted and diffused for creating the p doped base layer 4. The n+ source layer 3 is then created by implanting and diffusing an N-dopant using a resist mask. Subsequently, an oxide film is applied over the source layer 3 and partly over the base layer 4 for etching openings for the trench gate electrodes 7, which extend in depth direction down to the drift layer 5. Now a P dopant is implanted in the bottom of the trench. Then the oxide film is etched away and a thermal oxide film (for forming the insulating layer 72) is formed on the surface of the trenches, which are then filled with polysilicon doped with N-impurities for creating an electrically conductive gate layer 70. The polysilicon is etched back to the openings of the trenches, leaving the polysilicon buried in the trenches. Then the surface is covered by a second insulating layer 74, which is afterwards covered by a resist layer as another mask, which covers the regions on top of the trenches, the source regions 3 besides a small open area, which lies directly adjacent to the base layer 4 which is also uncovered. The second insulating layer 74 is then etched away at the uncovered resist mask areas, thus maintaining the second insulating layer 74 on top of the gate layer 70 and the adjacent part of the source layer 3. Afterwards AlSi is applied on the uncovered areas of the second insulating layer 74, by which AlSi layer, which forms the emitter electrode 2, the base layer 4 and source layer 3 are shorted.
The n-type enhancement layer 95 improves the PIN effect, increases the plasma concentration and lowers the on-state losses. However, such a prior art device having a highly doped enhancement layer 95 will suffer from worse SOA and breakdown voltage compared to standard trench IGBTs. As the carrier concentration near the active cell is enhanced by such an enhancement layer 95, IGBTs with such an enhancement layer 95 are superior compared to prior art IGBTs having no enhancement layer in view of higher safe operating area (SOA) and lower on-state losses.
However, the electric field at the n-enhancement/p-base junction 95, 4 also increases. Practical enhancement layer doping concentrations are therefore limited to values smaller than 2.5*1016 cm−3 to prevent excessive electric fields and therefore degradation of the blocking performance and turn-off SOA. As shown in FIG. 3, the on-state voltage VCE.on advantageously decreases for higher doping concentrations. That means for the breakdown voltage, the lower the doping concentration of the enhancement layer the better, and for the on-state voltage vice versa with an upper limit of the doping concentration at the point at which the breakdown voltage collapses.
The enhancement layer allows for a remarkable reduction of the on-state (vCE.on) and its benefits are even more important for larger doping concentrations of the enhancement layer 95 (ND,enh). However, the larger the enhancement doping concentration is, the lower is the breakdown voltage (VBD) that the IGBT is able to sustain.
FIG. 4 shows data for different prior art devices. Device 1 is a trench IGBT having a maximum doping concentration in the enhancement layer 95 of 2*1016 cm−3 and no first protection pillow. Device 2 differs from device 1 by having a first p doped protection pillow 8. Device 3 is a trench IGBT having a maximum doping concentration in the enhancement layer 95 of 1*1017 cm−3 and no first protection pillow, and device 4 differs from device 3 by having a first p doped protection pillow 8. In all figures, in which device 1-4 are mentioned, the devices shall be the devices with the features mentioned above.
The impact ionization effect, responsible for the detrimental degradation of the IGBT devices, is normally taking place at the trench bottom. However, in a device with an increased enhancement doping concentration (larger than 2.5*1016 cm−3) the avalanche generation takes place at the interface between the p-body and the n-enhancement regions. In order to be able of exploiting the on-state benefits of a highly doped enhancement layer, without suffering from the drawbacks of reduced RBSOA capabilities, a first p doped protection pillow 8 has been introduced in EP 0 795 911 A2. The first protection pillow 8 reduces the high electric field at the trench bottom, which have been created due to the introduction of the enhancement layer 95, so that the reverse blocking SOA and breakdown voltage VBD is improved. This is shown in FIG. 4, in which both devices having a first protection pillow 8 have an improved VBD, but worser VCE.OR. Nevertheless, the introduction of p doped first protection pillows at the trench bottoms improves the device robustness, being able to postpone the onset of the breakdown mechanism, but is not able to redeem the inherent weakness of a trench IGBT device sufficiently where the impact ionization is caused by increased enhancement doping concentration.
This is the case, because for devices with larger enhancement doping concentration levels, when the breakdown conditions are fulfilled the avalanche generation still takes place at the n-enhancement/p-base layer boundary, with a relevant amount of generated carriers near the Silicon/gate oxide (first insulating layer 72) interface. This potentially translates in unwanted drawbacks such as hot carrier injection in the gate oxide with consequent threshold voltage instabilities. Eventually, this device also shows a degraded dynamic avalanche robustness, and this phenomena is even more exacerbated under hard switching conditions as shown in FIG. 5.
Introduction of a first protection pillow to a prior art device having an enhancement layer of increased maximum doping concentration (i.e. above 2.5 or 3*1016 cm−3) leads to a great improve on the breakdown voltage, but still this values stays much lower than for a device without first protection pillow and lower enhancement doping concentration (i.e. below 2.5*1016 cm−3).
The p first protection pillow improves the breakdown robustness at the price of an increased on-state. However the weakness of avalanche generation at the enhancement/channel interface is present in the prior art device 4 with increased ND.cnh (FIG. 5). The hard switching turn off behavior of a prior art trench IGBT (dashed lines in the figure) and the Trench with increased maximum doping concentration in the enhancement layer and p+ first protection pillow 8 (alternating dashed/dotted lines in the figure) is shown in FIG. 5. Device 4 suffers from larger dynamic avalanche, as shown from the larger bending trend of the curves under hard switching conditions.
JP 2010 232627 A concerns a method for creating a trench IGBT. First a trench is etched into a substrate, which is then filled with an Arsenic epitaxial layer as n dopant. A heat treatment is performed, thereby creating a diffused epitaxial layer, which has a constant doping concentration along the lateral sides of the trench in depth direction. Afterwards the trench depth is increased and Boron is implanted and diffused at the deepened trench bottom.
US 2011/233728 A 1 describes a manufacturing method for an IGBT, in which a trench recess is etched into a drift layer, at the bottom an n dopant is implanted and diffused to form a contiguous layer as one n dopant layer. Afterwards, a p dopant is implanted in the same trench recess to form a protection region at the trench bottom, which is embedded in the enhancement layer.